Most integrated circuits such as a microprocessor consist of multiple circuit elements fabricated on a semiconductor material such as silicon. Generally, a clock signal is routed to many, if not most, of the circuit elements. This clock signal is used for the timing of the circuit elements.
The current trends in integrated circuit design are toward smaller device dimensions, higher levels of integration, and higher operating frequencies. Unfortunately, these trends tend to increase clocking inaccuracies. In order to meet narrowed timing requirements associated with higher operating frequencies, it would be desirable to not only prevent increased clocking inaccuracies, but to decrease clocking inaccuracies. Thus, generating and distributing highly accurate and stable clocks on a large integrated die present a challenge.
One method to manage and lower clock inaccuracies is to incorporate a Digital De-skew System (DDS) in the-global clock distribution of an integrated circuit. The integrated circuit die is typically divided into domains. A DDS is then inserted between domains to dynamically or statically lower the clock skew between them. A DDS typically consists of phase detectors, buffer control circuits, and adjustable buffers distributed throughout a clock distribution structure. FIG. 1 shows an example of such a DDS in a global clock distribution of an integrated circuit. The phase detectors 110–116 measure the phase error between two clocks and generate lead/lag signals depending on the relationship between the two clocks. The lead/lad signals are then processed by buffer control circuits which control the adjustable buffers 128–133, 143, 145, 155–157, 159–161.
Existing DDS' typically suffer from at least three problems. A first problem is that the generated delays from the adjustable buffers are not linear. FIG. 2 shows a graph of an output 215 of a nonlinear delay buffer. The y-axis 205 represents adjustable delay steps of the buffer measured in picoseconds. The x-axis 210 represents control bits that adjust the buffer. In order to achieve stability and convergence within a DDS, the delay steps of the buffer should be linear. Output 215, however, is not linear; delay steps gradually decrease as the control bit value asserted increases. Nonlinearity decreases the controllable delay range of the buffer.
A second problem is metastability and dither. Metastability may occur when a phase detector detects two perfectly aligned incoming clocks under ideal conditions. In contrast, dither may occur when the phase detector detects a phase difference between two clocks, but the delay step is too large to correct the difference between the two clocks. Thus, the phase error between the two clocks toggle around an equilibrium point.
A third problem is jitter when updates occur. Jitter is any cycle to cycle variation in a clock. In general, the larger the change in generated delays, the larger the resulting clock jitter.
Therefore, it would be desirable for a DDS to generate linear delays having a wide controllable delay range, detect phase differences without being susceptible to metastability and dither, and prevent large sudden changes in generated delays.